Typically, memory, e.g., Dynamic Random Access Memory (DRAM), and logic technologies have evolved along separate but parallel paths. In memory technology, for any particular lithography and power supply voltage level generation, the gate oxide thickness is limited by thin oxide reliability due to the stress of voltage boosted word lines. In contrast, for logic technology, thinner gate oxide thicknesses are generally the standard because of the need for high transconductance at lower internal operating voltages. Therefore, efforts to merge the technologies of memory and logic onto a single chip to create a “system on a chip” or other high function memory thus create a dilemma. That is, one is faced with the design choice of either (1) compromising the gate oxide thickness for one and/or both types of devices or (2) assuming the litany of complexities and expenses associated with the growing of two separate types of gate oxides on a single chip.
One current approach has been proposed that does provide a method of fabrication which allows for the scalable gate oxide thicknesses by either implanting Ar+ or N+ into a substrate prior to oxidation or implanting O+ into the substrate after gate deposition. While this approach does facilitate gate oxide scalability when compared to conventional process integration, this technique does not provide a total solution since additional steps as well as expensive process tools are required. Accordingly, more advanced methods are still needed for providing multiple gate oxide thicknesses on a single chip. Desirably these more advanced methods will use existing MOSFET and DRAM processing techniques, thus avoiding any additional complexity in the wafer fabrication process. For these and other reasons there is a need for the present invention.